The Paul Allen Center for Integrated Systems (CIS) was built in 1985. It provides an academic environment for advanced research on new devices and processing steps. CIS was funded by twenty founding industrial companies, which are still strongly active in supporting academic research at Stanford. Several companies started at CIS; among them were MIPS and Yahoo.

CIS contains the largest academic clean room in the Bay area. Almost from the start of CIS, it has also housed the Stanford Art Spaces exhibits. Together, they provide a striking juxtaposition of art and technology.


Through the windows you can see a clean room for nano-processing.

Semiconductor: Material intermediate between an electrical conductor (like copper) and an electrical insulator (like glass).

Nanometer: 10-9 meters. A human hair is about 100,000 nanometers in diameter. A red blood cell is about 8,000 nanometers. An atom of silicon is approximately 1/3 of a nanometer.

Every 8 seconds, the entire air volume of this room is circulated out to large air ducts, like the meter-wide duct just behind the glass. From there the air flows up to the third floor, down through filters on the second floor, and then back into the clean room through the ceiling. People inside the room wear “bunny suits” to minimize the release of human particles into the air. The result is that each cubic foot of air has fewer than 100 particles of size 500 nanometers, much cleaner than the air in a hospital operating room.

The 10,500 square feet clean room is vibration-isolated from the rest of the building. Support equipment, such as chilled water, vacuum pumps, air compressors, and acid waste neutralizers, are located in the basement. Corrosive and toxic gases are in a monitored gas area. Liquid gas storage tanks, emergency power generators, and a de-ionized water plant are outdoors. For more information, see SNF and CIS.


Deposition and removal: Materials may be added to the surface. Typical materials are crystalline silicon, amorphous (non-crystalline) silicon, or metals. Conversely, material may be removed from the surface. These operations are done in the Etching / Metal Deposition sections of the clean room as shown on the floor plan.

Modification: Heating the wafer in the presence of oxygen causes the surface to be oxidized. Bombarding the wafer with ions of specific elements implants the ions into the material. Layers of different material can be meshed by heating the wafer so that the atoms diffuse very short distances. These operations are done in the Diffusion / Oxidation sections of the clean room as shown on the floor plan.

Characterization: Some equipment may be used to precisely measure the intermediate and final results of fabrication.


Nano-fabrication uses a sequence of processing steps to build devices on a wafer.
The wafers are not made at CIS. A crystal of pure silicon (or germanium, or gallium arsenide) is grown, sliced into circular wafers about 1 millimeter thick, and polished. Equipment at CIS can process wafers up to 4 inches in diameter.

Patterning controls the shapes generated by the other processes. Patterning operations are done in the E-Beam, Mask Making, and Lithography sections of the clean room as shown on the floor plan.
Detailed patterns of lines and areas can be generated directly with electron beams or lasers, or they can be generated indirectly by first creating photographic masks and then shining light through these masks. The patterns are applied to a thin chemical layer which is subsequently developed (like a photograph) and washed, either to remove the exposed or the non-exposed areas.

The combination of one pattern with several processes creates a layer.
A wafer may have 20 or more layers, each typically 1 to 100 nanometers thick. (The overall process is roughly analogous to printing a magazine with four layers of colored ink.) For nano-devices, the patterns have features as small as 10 nanometers. For electronic devices, the patterns have features as small as 200 nanometers. For micro-electronic mechanical (MEMS) devices, the features are typically larger than 1,500 nanometers.

Although the wafer is 4 inches in diameter, the patterns are typically about 1/2 inch in size, with the same pattern repeated perhaps 100 times to represent 100 identical chips on the same wafer.
When all layers are finished, the wafer is diced into separate chips which may then be mounted, wired, and used.

Each chip may contain millions of devices.

Return to Stanford Art Spaces.