The CIS Newsletter

The Center for Integrated Systems, Stanford University
Stanford, California

Summer 1998

	Hitachi Joins CIS
	from Bob Dutton: Off the Roadmap: Research in Semiconductors
	CIS in Action
	Richard Dasher: CIS as a Global Organization
	Alumni Spotlight: Derek Shaeffer

CIS Signing Ceremony at Hitachi CRL: Front: Dean John L. Hennessy, Dr. Michiharu Nakamura Rear: Dr. Koichi Seki, Dr. katsuhiro Shimohigashi Dr. Richard B. Dasher, Mr. Carmine L. Salvucci, Dr. Tadashi Ikeda

Hitachi, Ltd. tracing its root back to 1910, one of the largest industrial corporations in the world, has become the newest partner company of the Center for Integrated Systems, with, Dr. Michiharu Nakamura, Director of Hitachi, Ltd. and General Manager of Central Research Laboratory, serving on the CIS Advisory Committee.

Headquartered in Tokyo, Japan, the company employs approximately 330,000 people worldwide including employees of major consolidated affiliated companies. Hitachi manufactures various kinds of products ranging from power systems, information systems, electronics, industrial and infrastructure equipment, to consumer products. 1997 net sales were approximately $69,000 million on consolidated base.

"Hitachi has a long history of research collaboration with Stanford University from the early 1960s, and holds the annual Hitachi-Stanford University seminar in CIS in February since 1984," said Dr. Nakamura. "Hitachi is looking forward to working with the faculty and people associated with CIS. Being involved in CIS as a full member will undoubtedly beneficial to Hitachi, and through this collaboration, relationship between CIS and Hitachi will be further strengthened."

Overview

In the 21st century, we will rely increasingly on technology, and Hitachi is well positioned for this reality. Hitachi's mainframes, workstations and state-of-the-art microchips have established Hitachi as one of the world leaders in the production of information and electronics products. In the field of semiconductors, despite continued demand for PCs, surplus supply lowered prices of DRAMs and other memory products. In this environment, Hitachi has been aiming well-balanced products lineup with higher value. Hitachi provided SH-3 RISC icroprocessors for handheld PCs using the new operating systems.

To promote these RISC processors, Hitachi licensed the RISC engine to several leading companies for use in their ASIC and multimedia products. In memories, Hitachi has been strengthening faster memory interface technologies for synchronous 64-megabit DRAM and high-density 64-megabit flash memory and memory cards, in which Hitachi's original AND-type memory cells, are utilized. In addition, Hitachi has already developed a technology to extract maximum performance by mixing DRAM and logic on a single chip, and released the HG73M series, which can include large-capacity DRAM modules up to a maximum 140 megabit and high-speed logic. With a wealth of accumulated technological expertise, Hitachi has the solutions for the next century.

Policy of Research and Development

Hitachi has always focused on R&D that covers a broad range of fields as a driving force for ensuring competitiveness in business. Nearly 16,900 Hitachi researchers in 32 laboratories are engaged in a wide range of ongoing studies in the fields of electronics, software, energy, and new materials, both at the fundamental research and application levels. Also, Hitachi is expanding its overseas R&D presence as part of its globalization. Hitachi has established R&D centers in Europe, U. S. A. and recently in Asia, which are geared to developing products best suited to local needs and create seeds for the future. Dr. Nakamura comments, "Our aim is to develop a new industrial frontier through our endeavors in research, which extend from the development of new scientific technologies to their practical application. We put a special emphasis on the creation of new technological trends and the speedy transfer of new technology to commercial products."

For more information, visit Hitachi's homepage at http://www.hitachi.com/

from Bob Dutton

T he summer is a welcome "breather" from what has been a very challenging year for restructuring of many of our research plans at CIS as well as the ongoing building projects of the new Science and Engineering Quad along with the efforts to recruit new faculty to fill many current and projected retirements in the Electrical Engineering Department. After giving a brief snap-shot of progress in research customization, I would like to discuss a very pressing concern related to the longer-term outlook for semiconductor research at CIS.

Research customization

As discussed in the Spring Newsletter, the process of Research Customization is moving forward steadily and we continue to be both excited and encouraged by the very constructive way that our partners are considering specific investments in people and projects. The one-on-one discussions with our CIS partners, while somewhat more time consuming than block funding (based on "requests for proposals"--RFPs), is definitely creating greater research diversity in the CIS program. The ability of our sponsors to choose novel projects that reflect their interests is being reflected in unique and new directions for the CIS program. One example that has grown, step-by-step in importance and potential impact, is the area of process and device modeling for trench isolated ICs, including but not limited to shallow trenches (so-called STI technology). Starting with the lead of AMD to focus their funds in new simulation capabilities to model stress, other sponsors have expressed growing interest and added critical resources to create a mini-focus- project in this area. Applied Materials (AMT) is now collaborating with our researchers and learning to exploit the unique capabilitieof coupled process/device modeling to provide better process flows and process "windows" for trench-isolated structures. Moreover, our newest CIS member Hitachi (see cover article), has also opened an active dialog about fundamental issues related to leakage along trench surfaces. These are an interesting representative set of collaborators and each brings very different and complementary expertise to our research program---logic and RAM applications as well as key manufacturing know-how. Moreover, as discussed below, the ongoing shifts of other research funding sources away from CAD for silicon process modeling has opened the door for more creative new "mini-consortia"-like groups to focus their interests and resources.

There are certainly many other exciting examples that cross-cut the spectrum of CIS Thrust Research Areas (http://www-cis.stanford.edu/research/thrusts.html). At the systems level there is ongoing and growing enthusiasm for network (including wireless) projects as well as graphics related themes--pixels through how to sustain memory bandwidth. Circuits related projects continue to grow and flourish, including fundamental modeling challenges (i.e. noise, distortion etc.) facing RF designers. National Semiconductor is now generously providing several key universities including Stanford, access to advanced 0.25um technology on a quick-turn-around basis. This kind of facilitated access is essential for experimental prototyping and nicely complements the Stanford Nano-Fab (SNF) facility that is considering alternative (MEMS) and ultra-scaled processes (beyond NTRS).

Off the roadmap

Having now spoken the "roadmap" word (National Technology Roadmap for Semiconductors--NTRS), I would like to briefly consider the growing challenges facing the university community, resulting from marginalizing research that "doesn't fit the NTRS". In spite of strong support from many of our CIS partners to promote longer-range research using industrially funded projects, the territorial imperative of the NTRS has in many ways resulted in reduced semiconductor research funding both for topics on- and off-the-roadmap. The assumption from many of the Offices of Research--major agencies (i.e. DARPA) and services within DoD (i.e. ARO, ONR...)--is that since the semiconductor industry has such a roadmap and money to fund it, incremental DoD funding will have marginal (if any) impact.

While in general there are positive trends in federal research funding, including DARPA and NSF, the focus is shifting--for example into bio-science related areas. Conversely, the reality of funding through the semiconductor industry and specifically SRC is often that the goals are short-term and the canonical question seems to be, "how does this work fit on the NTRS?"

To non-traditional paths?

The changing scene in government (especially DoD and NSF) funding will not likely be moving further in the "traditional areas" of interest to semiconductor companies, but rather in the "future" areas of telecom, software, wire-less systems, networks and farther out technologies such as bio-tech and bio-electronics. Even the existing faculty in these "traditional areas" are moving on and adapting to the changing times. Hence, the opportunity to continue to hold mind-share with students and faculty will depend critically not on Roadmaps of what the semiconductor industry needs, but rather real (and sustained) support that will stimulate long-term interest of the researchers.

To give one sampling of recent trends in how students interests are changing, under the new Stanford Graduate Fellowship program and among the more than twenty new students currently at Stanford in EE with that sponsorship, few of them have chosen to affiliate with SRC programs. The majority are working in the "new" areas of EE. These are presumably our "best and the brightest" next generation. According to Jim Plummer, Department Chairman for Electrical Engineering, "...a possible reason they have not chosen to affiliate with SRC or semiconductor industry research programs, is fundamentally because many of those programs are so NTRS driven that they are not 'exciting' or long range enough for our best students." There is a consensus among many others here at CIS that the semiconductor industry should be concerned about these kinds of trends.

Ending on a more positive note regarding semiconductor-related research, there are a few new venues in simulations and modeling that offer long-term promise. Certainly the National Science Foundation (NSF) is supporting essential infra-structure and research-- National Nanofabrication (NNUN), National Science Alliance (NCSA) and National Computational Electronics (NCCE). Stanford and CIS-based activities are connected to all of these national efforts, and the research is expected to grow and be more leveraged in the future. Finally, I would like to share a recent experience I had in visiting the local NASA Ames facility that provided a refreshing oasis.

At the end of June I had the pleasure of joining a review panel for a NASA-funded nano-technology modeling program, Integrated Product Team (IPT) working on Devices and Nano-technology (IPT) (http:www.ipt.arc.nasa.gov). The Ames Research Center Director, Dr. Henry McDonald, invited an outside panel to give the IPT feedback on the overall research program and ways to enhance both the quality and impact. The scientific depth and breadth of these modeling efforts was extremely impressive and in fact posed modeling and technology problems that include: computational chemistry, device physics and simulation, carbon nano-tube technology and plasma equipment modeling. NASA has a very positive view of interactions with industrial consortia such as SRC, and in fact has entered into a memo-of-understanding (MOU) to exchange/transfer research results. They also have created an environment that both encourages and strongly supports academic collaborations. In short, they are doing good science in long-term directions that benefit the future of semiconductor devices and technology. Moreover, the spirit and style with which they are addressing this work matches very well with that of academia. In summary, there are exciting developments in our CIS research program, especially in the new emerging customization projects that are being launched in coordination with our CIS partners. Unfortunately, there continues to be a "marginalization" of semiconductor research based on a (false) perception that having a Roadmap implies that someone else will fund it.

Finally, I've highlighted both NSF-sponsored national centers and the NASA Ames IPT project as oasis that support longer-range research that can impact positively future advances in semiconductor devices and technology--defined in a much broader sense.

Dr. Ron Knepper, 2nd from left, leads IBM Staff in hosting SPIE Team visit headed by Prof. Robert Dutton and Dr. Richard Dasher.
CIS SPIE team member, Bendik Kleveland meeting with IBM technical staff. Led by Jeff Welser, CIS Alum on the right at T.J. Watson Research Center, New York.	Session at the CIS Advisory Committee Meeting, April 22, 1998.
EE201B Seminar students visit Advanced Micro Devices, Santa Clara on March 6, 1998 for a tour of the facility.

by: Richard Dasher
Executive Director

C IS has long prided itself on world-class graduates and world-class research. As we welcome Hitachi Ltd., our first partner company from Asia, it is useful to take a few moments to think about the implications of CIS itself becoming a global organization.

First of all, the worldwide membership of CIS is a striking indication of how high technology industries have changed over the last fifteen years. I was working for the U.S. State Department in Japan in the mid-1980s, and so I remember well many briefings and first-hand stories about the difficult negotiations over the first U.S.-Japan semiconductor agreement. A worldwide partnership to support leading edge research in semiconductors, electronics, and computer systems would certainly have been unheard-of in those days.

These days however, intense global competition means that companies must look worldwide to find the best R&D partners, locate the best sites for manufacturing, and coordinate global product and technology management strategies. A glance at business news reveals at least one or two major new international cross-firm alliances each week. CIS likewise needs to have all the best players present at the table in order for our partner companies and our faculty to engage in truly meaningful discussions of research directions, different technical approaches, and other mutual concerns.

Worldwide membership, however, provides additional challenges to CIS. Different countries have very different traditions in regard to industry-university interaction. These include major differences in regard to ownership of research results, administrative procedures and budget years, and direct enrollment by company employees in university Ph.D. programs, to name just a few issues. Some of the benefits and constraints of CIS membership could be left to implicit understanding in earlier times, but they must now be overtly specified in order to avoid misunderstanding and inaccurate expectations among current and prospective partner companies from such different traditions. A further challenge for CIS is to provide even more diverse opportunities for mutual sharing of information and expertise. Worldwide membership exacerbates the differences in geographic constraints that have always existed among our various partner companies. For example, Ph.D. recruiting opportunities may be of less interest to overseas partners than are other CIS benefits (although we always stand ready to assist any partner company in arranging recruiting activities here). How can CIS engage our distant partner companies through channels of interaction that are sufficient to justify the costs and expectations that membership entails? Fortunately, CIS has much experience in ensuring that membership benefits can be enjoyed by our geographically remote partner companies as well as by our partners who are close-by. We have also taken some important steps to increase the channels for interaction. Some involve the use of information technologies. Since last year, we have begun systematically placing A/V materials from CIS-related Ph.D. oral presentations and posterboards onto our Internet web site, http://www-cis.stanford.edu. (Since these materials are on a members-only page, please contact us if you have difficulty downloading it.) This summer, we are beginning a program of sending videotapes of selected Ph.D. oral presentations to our partner companies. Other channels will involve direct student-partner company interaction. One of our targets for the coming year is to increase our emphasis on summer internship opportunities at our partner companies.

The success of the CIS partnership has always derived from mutual sharing of information and insight between our partner companies and the University, not from a one way flow of information or technology. It is through this mutual exchange that CIS will continue to grow both as a global organization, and as a forum for world-class cooperation.

MH:   How did you become an electrical engineer?
DS:   Well, my Mom is an electrical engineer and my Dad's a physicist, so it's kind of in my blood. Also, when I was 8 or 9 years old, I made a crystal radio from a kit; I hooked it up to the faucet of the kitchen sink and got pretty good reception. But, I really didn't decide on electrical engineering until I was in college.

MH:   Any special reason you come to Stanford for grad school?
DS:   Stanford had the best combination of environment, quality of life outside of classes, and opportunities to pursue different avenues of research. I was fortunate to meet Prof. Tom Lee early on, and later I was the first person to join his group. I liked the idea of seeing the group from the beginning; it was risky and exciting. And, it's been really fun to see the group take off.

MH:   Let's talk about your research.
DS:   The thrust of my research is related to CMOS and low noise amplifiers. When I started out I found that some aspects of low noise amplifiers and CMOS had been neglected for years, in particular a phenomenon known as induced gate noise. By incorporating this effect, I was able to create an optimization procedure to achieve the best noise performance to date for a CMOS LNA. The other part of my work is on low power CMOS radio receivers. We set out to implement a GPS receiver with a higher level of integration and superior performance compared to commercial integrated GPS receivers. And, we wanted to do this in a cheap CMOS technology in a short time with a team of eight graduate students. Our team knocked out a GPS receiver that consumes just over 100mW in only four and a half months.

MH:   Can you recall some of the toughest problems you faced?
DS:   Well, some of them had to do with CMOS models. We had to identify a good simulator system. RF CMOS modeling is an interesting area, and I think that there will be a lot of this research at Stanford in the future. Another new experience for me was managing the team of students who worked on the GPS receiver. It's a challenge to make sure that morale is up and to try to meet the schedule.

MH:   How did the CIS partners help?
DS:   Besides CIS financial support, one of the partner companies, Rockwell International, provided us with foundry services. My contact there, Christopher Hull, was very helpful. What worked well with the Rockwell relationship was that we had someone there who was very supportive of Stanford and who would grease the skids for us to get things done. We had a really good exchange, and I think the work definitely shows it.

MH:   What is happening in the group now?
DS:   We have some fundamental work on phase noise in oscillators, spiral inductors and transformers, and optimization techniques for automated synthesis of circuit blocks. We also have some implementational work on a 5GHz wireless LAN receiver in CMOS. Other topics range from high-speed (10Gb/s) serial links to biotelemetry, digital coding techniques, and power amplifiers. Overall, Tom Lee is our coach and our central resource for getting good research done. He's also our radio historian with an endless supply of anecdotes.

MH:   What about your future?
DS:   Well, I have a job lined up in industry for now, but I have always loved teaching and admired excellent teachers. ..

Derek's dissertation, The Design and Implementation of Low Power CMOS Radio Receivers was submitted to the University in August 1998. You can view AV materials from his oral exam presentation at http://cis.stanford.edu/programs/talks/shaeffer/abstract.pdf

Please contact your CIS Advisory Committee representative for a copy of the videotape of that presentation.

Please send comments, suggestions to: maureen@cis.stanford.edu

Updated 9/24/98