First, let me enthusiastically introduce Dr. Richard Dasher as our new Executive Director of CIS. Richard comes to us with an impressive background and set of experiences related to management of technology. He will give you a brief retrospective on those experiences and how they most certainly will give a special push to CIS activities going forwards. I am delighted to have Richard on board; we are using this opportunity to visit all our partners and recalibrate goals and objectives in the partnership – customization being a key part of that agenda.

At the Fall Advisory Committee Meeting our CIS partners strongly supported our proposal to customize a significant fraction (nearly 1/3 of the Center’s total research budget) towards projects that are directly selected by the member companies. We are now actively working with our partners in facilitating those selections, including the critical team building on both academic and industrial sides. All CIS members have access to the research results generated in the customized projects as well as all other seed projects and students that are funded by CIS. The key difference with customization of research is the one-on-one dialog as opposed to a less flexible consensus process that can overlook many promising topics that might be of high priority to a few sponsors. We expect to highlight the selected projects in forthcoming issues of the Newsletter. However, based on discussions to date with several partner companies it is clear that we will see some very exciting developments that can have a long-term positive impact on the CIS research agenda. In fact, the balance between long-term and shorter-term strategic research deserves special comment and discussion.

The challenges facing corporate R&D organizations are formidable. For example, the cost of technology development for ~100nm devices requires major capital expenditures, setting bounds on expected ROI as well. Similarly, generating chip designs (and IP) that can fully exploit state-of-the-art IC fabs is of equal concern. Above and beyond these issues are looming challenges such as availability of lithography tools to pattern ~100nm devices and limits in scaling junctions and contact resistance. Hence, the options to look forward several generations in technology (near the end of the Road Map) or at circuits and architectures that could exploit such technology shifts seems nearly a luxury. However, there is good news to report (a "double happiness") in the "marriage" being renewed with many of our CIS partners in both their research vision and commitment to support paradigm shifts through CIS research funding. There is growing evidence that in contrast to consensus management that seeks common ground (that "plays it safe"), partners are willing to fund projects that focus on goals worthy of the best and brightest across the research boundaries of academia and industry. Project by project, our corporate sponsors are voting for higher risk, long-term research options.

It would indeed be exciting to conclude that the future is brighter than ever for advanced semiconductor and systems research in academia. From the perspective of vision and vibrancy, the research opportunities on the horizon are most exciting. Despite the challenges of cost (of technology) and design complexity (for systems-on-a-chip), new generations of students are eager to tackle atomic-scale technology and giga-scale (clock frequency and functional complexity) architectures. As a footnote, please see Bill Dally’s exciting vision. Yet at both extremes–devices and chip designs- – these are by no means commodities readily "off the shelf". Moreover, despite the very promising trends mentioned above (i.e. willingness of corporate sponsors to explore higher risk options) there is a critical need for renewed leadership (and funding) in support of such advanced research and experimental prototyping. Partners are willing to collaborate in test chip prototyping, a very promising trend. Nonetheless, the overarching government support, both in education and experimental training, now seriously underestimates the strategic needs and opportunities that lie ahead.

We look forward to showcasing the customized research projects and research teams in the forthcoming issues. Also, the process of selection and vision provided by our CIS partners is essential; several companies have agreed to share their views on leading research challenges. We are delighted to share this dialog and deeper or common understanding.

by William Dally
Prof. of EE and CS

Most importantly, conventional full-swing signaling does not scale with improving semiconductor technology. Because transitions must ring out over several round-trips of the unterminated lines, signaling rates are limited by the length of the wires, not the speed of the devices. This is the reason why microprocessors that use conventional signaling operate their external buses at a small fraction of their internal clock rate.

Our research here at Stanford has put off-chip signaling back on a Moore’s law curve while at the same time lowering power and improving noise isolation. Sending low-swing signals and terminating lines into a matched impedance gives a signaling system that operates using only the incident wave of a signal. Because there are no appreciable reflections, the bit rate of these signaling systems scales with the devices and is not limited, to first order, by wire length. Maximum bit rate is set by the stability of the timing circuits, the transition time of the transmitter, and the aperture time of the receiver. All three of these factors improve linearly with gate length. In an 0.5mm CMOS process we have demonstrated an I/O pad that operates at 4Gbits/s. We expect to be able to achieve nearly twice this rate in an 0.25mm process.

Switching from full-swing signaling, which is limited to about 100Mbits/s, to incident wave signaling at 4Gbits/s has a dramatic and enabling effect on system architecture. Systems that demand very high-bandwidth between processor and memory or between pipeline stages partitioned across chips become feasible with this 40x improvement. At the same time, traditional bus-structured architectures must be abandoned in favor of more robust network architectures because incident-wave signaling is limited to point-to-point links.

Equalization is needed at these very high bit rates to compensate for the frequency-dependent attenuation of all but the shortest wires. An 0.5m PC board trace, 5m or 24-gauge twisted pair, or 20m of RG59 coax will attenuate the high-frequency components of the signal to the point where the unattenuated low-frequency components cause unacceptable interference. To solve this problem, we have adapted equalization methods, long used in modems at kilobit rates, to operate at gigabit rates. The results are shown in the two scope photos. The isolated pulse on the left is badly attenuated. By preemphasizing the high-frequency component of the signal with a digital filter, the pulse on the right is completely restored.

As technology continues to evolve, on-chip interconnect will become the critical factor in system design. Today, the reach (the distance a signal can be transmitted over a wire in a single clock cycle) of an 0.25mm chip with a 500MHz clock is about 10mm, and it takes 2 cycles to transmit a bit from corner to corner on a large chip. By 2007, the reach of an 0.1mm chip with a 2GHz clock will be 2mm and it will take over 20 clock cycles to move information from one corner of a chip to the opposite corner.

(d) with equalization, the lone 1 pulse is cleanly detected.

To make efficient use of future technology we must develop architectures that minimize the effect of slow wires by making communication explicit and optimizing its use. Contemporary superscalar architectures, in contrast require global communication for both data and control, and hence will not scale well with improving technology. We are currently exploring architectures that exploit locality to make the best use of wire-limited technology. By tailoring the architecture to the bandwidth and latency properties of the technology we can take advantage of the rapidly increasing speed and density of devices while minimizing the impact of slow wires.

Background

Professor Dally joined Stanford in the Fall of 1997 after teaching for 11 years at MIT. His research explores parallel computer architecture, graphics hardware, and the digital circuit technology demanded by these high-end systems. At MIT he led the development of the J-Machine and M-Machine parallel computer systems and developed simultaneous bi-directional signaling, gigabit rate equalized signaling, and methods for building fast synchronizers. He is an author of Digital Systems Engineering, a new text that describes the technology of high-performance digital systems.

Before coming to CIS, I have had the privilege of working with a number of outstanding teams in industry, government, and the academic community. From 1986-90, I directed the U.S. State Department*s Japanese and Korean language and area training centers located in Yokohama and Seoul, respectively. These centers, which are attached to the U.S. embassies in those countries, provide full-time training to U.S. and selected British Commonwealth country diplomats in advanced language skills and area knowledge. With top-class teachers and elite students, my challenge was to develop hands-on experiences to take maximum advantage of the unique opportunities of in-country training. I am proud to have negotiated new programs that earned the praise of Ambassador Mansfield for the effectiveness of our graduates. Subsequently, as a board director of two companies in Tokyo, I was able to broker successfully a number of new business relationships for European and American companies in the Japan market. I have been back at Stanford since 1993, developing new programs for the US-Japan Technology Management Center (USJTMC) in the School of Engineering.

Richard B. Dasher, Ph.D.

My experiences have shown me what managers everywhere know: there are two keys to the success of any collaborative project, namely (a) the abilities, dedication, and teamwork of the people involved, and (b) substantive interaction between the project team and their sponsoring organizations. This point has come across particularly clearly in our USJTMC programs. USJTMC public seminars and other programs have investigated research consortia, bilateral corporate alliances for R&D, government and industry-sponsored research programs in advanced electronics technologies, and related issues in technology transfer and intellectual property management on both sides of the Pacific. In every case, success has hinged on the quality of the team and its opportunities to provide added-value back to the project sponsors, as well as to receive their continuing support.

Now, as one of my first tasks at CIS, I am engaged in the thoroughly enjoyable task of getting to know the members of this outstanding university-industry partnership. The students, affiliated faculty, partner company representatives, and CIS staff have all impressed me in a very short time with credentials that are truly world-class and with their strong commitment to a common vision. This is not surprising: the success of the CIS partnership is well-documented, and recent announcements from CIS-supported research indicate exciting directions for the future.

With such a strong team already in place, the challenge for CIS is clearly to continue to develop even higher bandwidth connections for the reciprocal transfer of expertise, vision, and other benefits between the team at Stanford and our CIS industry partners. Like an engineering problem, this challenge requires us to continue to tweak the current framework for incremental improvements at the same time as we explore new solutions that may lead to paradigmatic breakthroughs.

CIS already has a number of excellent channels for university-partner interaction: FMA (Fellow/Mentor/Advisor) relationships, SPIE (Student-Partner Information Exchange) visits, visiting researcher opportunities, and CIS-sponsored thrust research serve as a model of university-industry collaboration that is nothing short of outstanding. Moreover, two new channels to increase the bandwidth of interaction are already in the final stages of development. As Bob Dutton outlines in this newsletter, we are moving forward with the exciting new component of research customization within the CIS research program. The CIS intellectual property agreement likewise clarifies another type of benefit transfer, namely guaranteed access for partner companies to the results of CIS-sponsored research.

Nevertheless, it will take frequent and candid communication, a philosophy of continuous improvement, and sustained effort to make sure that CIS keeps pace with our partners' changing needs and interests. As we increase the bandwidth of interaction, it also remains essential for everyone in the partnership to preserve the flexibility that has proven to be so productive in the past. The value in the vision of CIS faculty depends on their freedom to take the lead in defining new directions of research; at the same time, the unrestrained voices of our industry partners provide essential insight into the applications and expertise that industry needs. I am looking foward to working closely with each member of this outstanding team, and to developing even broader contacts with the organizations that stand behind this partnership. Please call on me at any time.

Dr. Mark E. Dean, a CIS alum who worked with Prof. David Dill and Prof. Mark Horowitz on "STRIP: A Self-Timed RISC Processor" from 1989 to 1992, was recently named Director of IBM's Austin Research Laboratory, and more recently demonstrated the world's first experimental CMOS microprocessor that can operate at one billion cycles per second (1000 MHz or 1 Ghz), developed using IBM's existing 0.25-micron CMOS 6X technology.

The microarchitecture, circuits and testing techniques resulting from this project will eventually be applied to microprocessors using IBM's future CMOS process technologies and its recently introduced "copper" technology.  "With this demonstration, we believe it is possible to design 1000 MHz products," said Dean. "Equally significant is the fact that we've developed the tools and insight that will be necessary to push this technology to even greater performance levels." The 1000 MHz chips were fabricated at IBM's Advanced Semiconductor Technology Center in East Fishkill, NY and tested at the T. J. Watson Research Center in Yorktown Heights, NY.

Dean remarked that "when I was accepted at Stanford I had been out of school for ten years, so it was very difficult. I encourage people to go on to graduate school, but they should not wait as long as I did. It makes it very hard, But for me it was definitely the right thing to do and Stanford was the right place to do it. In hindsight, Stanford was the best choice because I already knew what I wanted to work on and both David Dill and then Mark Horowitz enthusiastically supported me in pursuing the research tropic I wanted to work on. The research I engaged in as a graduate student was very prudent, in that while some of the technology isn’t necessarily what we are doing today, it did allow me to better understand the best ways (pros and cons of certain approaches) to approach the development of processes. I came to Stanford with no knowledge of either circuits or processes, I knew logic design, architectures, bus interfaces and protocol, but I had no real knowledge of transistors, silicon processes and circuits. Stanford was my first exposure to custom circuits design to building things at transistor level. I am now managing a group focused on high-speed circuit design and I couldn’t have done it without the background I received at Stanford."

In 1997, Dean, an IBM Fellow (IBM's highest technical honor) holding more than 20 patents, including three of IBM's original nine PC patents, received the Black Engineer of the Year President's Award; the Ronald H. Brown American Innovators Award; and was inducted into the National Inventor's Hall of Fame in Akron, Ohio, along with two other IBM colleagues (Robert H. Dennard and Dennis L. Moeller). To date, only 137 men and women are honored in the National Inventor's Hall of Fame. A member of the IBM Academy of Technology, Dean has received eight Invention Achievement Awards and six Corporate Awards.

Dean and Moeller developed improvements in computer architecture that allow IBM and IBM-compatible PCs to run high-performance software and work in tandem with peripheral devices. The work of Dean and Moeller has truly enhanced the agility of the PC by enabling components to communicate with each other in a high-speed and efficient manner. This technology was first integrated in IBM PCs in 1984, and is currently a key component for more than 40 million personal computers produced each year.

"We never looked at it as a revolutionary invention," said Dean. "We wanted a useful tool that would make designing reliable systems easier. As engineers, we recognized a need in the PC industry from which IBM customers would benefit."

Prior to his position with Austin Research, Dean was Vice President of Performance in IBM’s RS/6000 Division, Director of Systems Structure and performance for the IBM RS/6000 Division, and Vice President of System platform in IBM's Network Application Services Division, Interactive Broadband Services group, where he was responsible for IBM's video server offerings. Earlier, as director of architecture for the Power Personal System Division, Dean was responsible for creating the PowerPC Reference Platform specification.

Dean was born March 2, 1957, in Jefferson City, Tennessee. He received a BS in Electrical Engineering (EE) from the University of Tennessee in 1979, an MSEE in 1982 from Florida Atlantic University and a Ph.D. in EE from Stanford in 1992. He has been with IBM since 1980, and was named an IBM Fellow in 1995, one of only 50 active fellows of IBM's 200,000 employees. Dean was the first African-American to be honored with an IBM Fellowship.