For several decades, MOS technology has scaled according to "Moore's law," and it is expected that this scaling will continue for at least another decade. As a consequence of the scaling of CMOS technology, digital signal processing is becoming almost ubiquitous, and digital circuits will continue to benefit from the projected advances in technology.
It is not clear, however, that analog circuits will benefit from further technology scaling. Device scaling lowers the supply voltage, thereby leaving less headroom for design. Also, a lowered supply voltage means reduced dynamic range unless the noise floor is also reduced, which typically requires increased power dissipation. This situation will be exacerbated as state-of-the-art CMOS technologies enter the sub-1V supply regime.
Sigma-delta modulators are one of the circuits directly subject to the difficulties imposed by the continued scaling of technology. There have been efforts to develop low-voltage design techniques, such as switched-opamps techniques and sub-threshold (weak-inversion) designs. However, these approaches have been limited to relatively low-speed applications.
The objective of this research is to investigate means of building high-speed A/D converters based on the use of sigma-delta modulation. In particular, the work focuses on both architectural and circuit approaches to confront the hostile low-voltage analog design environment. A systematic means of minimized power dissipation in these circuits has been also developed.
To demonstrate the feasibility of building high-resolution, high-speed sigma-delta modulators that operate from a low supply voltage, an experimental prototype has been integrated in a 0.25-um technology. Operating at 1.2-V supply, it achieves a dynamic range of 96dB and a peak SNDR of 89dB for a signal bandwidth of 1.25MHz with the power dissipation of 87mW.
Integrated Circuits Lab
Center for Integrated Systems
Stanford University