Table of Contents
PPT Slide
Outline
Motivation
D/A Conversion
DT-CT Conversion
CMOS DAC Papers
Outline
Noise
Nonlinearity
Power
Outline
Traditional Architecture
Alternative Architecture
SD Modulator
Dynamic Range
Single-bit vs. Multi-bit
Linearization Techniques
Dynamic Element Matching
Current Calibration
Proposed Architecture
System Block Diagram
Outline
Digital Modulator
Pipelined Adder
Building Block #1
Building Block #2
Modulator Implementation
Frequency Spectrum
Tone Performance
Chip Floor Plan
PPT Slide
Non-idealities in DAC
PPT Slide
Timing Errors
Timing Errors (ctd.)
Clock Buffers
PPT Slide
Glitch Analysis
Glitch Analysis (ctd.)
Glitch Analysis
PPT Slide
PPT Slide
Driver Output (simulated)
Outline
Die Photo
Test Set-up
SNR/SNDR Plot
Performance Summary
Contribution
Acknowledgments
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Author: Katy Falakshahi
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