Interconnects for Nanoelectronics: 3-D Heterogeneous Integration

Continuous scaling of VLSI circuits can pose significant problems for interconnects, especially for those responsible for long distance communication on a high performance chip. Our modeling predicts that the situation is worse than anticipated in the ITRS, which assumes that the resistivity of copper will not change appreciably with scaling in the future. We show that resistance of interconnect wires in light of scaling induced increase in electron surface scattering, fractional cross section area occupied by the high resistivity barrier and realistic interconnect operation temperature will lead to a significant rise in the effective resistivity of Cu. As a result both power and delay of these interconnects is likely to rise significantly in the future. In the light of various metal interconnect limitations, alternate solutions need to be pursued. His group focuses on two such solutions, optical interconnects and three-dimensional (3-D) ICs with multiple active Si layers. His group is working on following projects:

NSF/SRC Center for Environmentally Benign Semiconductor Manufacturing

The purpose of this multi-university NSF/SRC Center is to create the science, technology, and educational methods to lead the semiconductor industry to a new era of environmentally benign manufacturing. Prof Saraswat is the Associate Director of the center and also leads the Stanford group consisting of Paul McIntyre (MS&E), Yoshio Nishi (EE) and Stacey Bent (Chem Eng) and is Associate Director of the whole Center. The specific goals of the Center are to:

AFFILIATED Ph.D. STUDENTS & VISITORS:

Hoon Cho
Research: Scalable Flash Memory Technologies. (PhD Sept. 2007)

This work is focused on development of novel flash cell devices. The objective is to have them scalable to small dimensions whereby they can be operated at lower voltages, while maintaining the current retention time and write/erase and read speeds. We have proposed novel device designs which incorporate a combination of innovative device structures and alternative materials. After having evaluated a design with simulations (MEDICI and TSUPREM4), we are currently in the process of developing the fabrication process.

Hoyeol Cho
Research: Performance comparison between high-speed electrical and optical interconnects for interchip communication (PhD March 2007)

Optical interconnects are still the most promising candidate to solve the challenges imposed by electrical wiring, both for off-chip and possibly on-chip application because of their low signal attenuation and cross-talk. As the computational bandwidth of the modern integrated circuits (ICs) (measured by the product of the number of transistors and the clock frequency) increases dramatically, electrical interconnect (copper traces) at short distances (chip to chip or board to board scale), at least in bandwidth sensitive applications, are struggling to keep up, rendering communication bandwidth a bottleneck. This presents a fertile ground for optical medium of communication to penetrate the short distance world, albeit with very different constraints compared to long-haul communication. Because the increasing power density and system bandwidth demands the insertion of optics to the short distance interconnects, a systematic and a realistic study of performance comparison between electrical and optical interconnects is of paramount importance. Such a comparison framework will give us the better idea of designing optical interconnects systems using optimized optoelectronic devices maximizing the system performance. Our framework included the device optimization at the both transmitter (modulator/VCSEL) and receiver ends (transimpedance receiver), showing that for bandwidth of 6Gb/s at 100nm technology node, lengths greater than the critical length of about 43cm yields lower power in optical interconnects. This length becomes lower (making optics more favorable) with technology scaling and higher data rates, close to 10cm at beyond 32nm technology node.

M. Gunhan Ertosun
Research: Novel Flash Memory Technologies

The most relevant phenomenon of this past decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipment (palm top, mobile PC, mp3 audio player, digital camera, and so on). Moreover, in the coming years, portable systems will demand even more nonvolatile memories, either with high density and very high writing throughput for data storage application or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility, and the cost make the Flash memory a largely utilized, well-consolidated, and mature technology for most of the nonvolatile memory applications. Today, Flash sales represent a considerable amount of the overall semiconductor market.
This research focuses on introducing new structures and/or materials so as to improve the conventional Flash device characteristics such as speed, power and scalability.

Sneha Gupta
Research: Multi-junction photovoltaics

With the continuous increase in worldÕs energy demand, fossil fuels are being depleted much faster than they are being formed. So, even with more efficient energy use and conservation, a transition to new sustainable energy source is required. Photovoltaics (PV) seems to be promising in this regard. PV power generation systems are clean, and utilize an inexhaustible and renewable energy source. However, high manufacturing costs have limited the sales potential. This work aims on achieving high efficiency device at a low cost, utilizing the multi-junction structures of silicon and germanium.

Jinendra Raja Jain
Research: Strained Ge bulk and GOI MOSFETy

As strain technology has significantly improved on-state characteristics for Si-based MOSFETs, strain may help Ge devices achieve higher than as-yet obtained mobilities. Modeling efforts are ongoing to study the electronic structure of strained Ge, while experiments to determine the quantitative effect of strain on Ge MOSFET performance are being defined. Several methods for introducing various types of strain in Ge channels are being explored for both bulk and GOI devices.

Crystal Kenney
Research: Implementation ohmic contacts to III-V material channel devices

As conventional CMOS technologies scale the importance of implementing new materials and structures is becoming more apparent. III-V materials such as InGaAs show promise as "new" materials due to their high electron mobilities. Therefore it may prove beneficial to implement an NFET device with a III-V material as the channel. Ohmic contact technology will need to improve to effectively introduce these new devices at smaller technology nodes. Future work includes identifying and addressing the obstacles of ohmic contacts to III-V channel devices.

Donghyun Kim
Research: Theoretical performance investigation on high mobility channel MOSFET devices

This work focuses on the study of the performance limits of ultra-thin body double-gated (DG) high mobility channel MOSFETs. Si, Ge, GaAs, InAs, InSb, InP, strained SiGe and strained InGaAs are being investigated under ballistic transport, taking into account full band structure, quantum effects, BTBT and SCE. Local empirical pseudopotential method is used to calculate the bandstructure of strained semiconductors. It becomes important to predict the band to band tunneling leakage of devices made with high-mobility materials. We have developed a BTBT model, which captures important quantum mechanical (QM) effects in nano-scaled DGFETs.

Eun Ji Kim
Jointly with Prof. Paul McIntyre (Materials Science and Engineering)
Research Topic: Interlayer and Defect Studies of High Permittivity Dielectric Layers on Si and Ge Substrates

This research is focused on the defects in the high-k layers on Si and Ge, their relation to the process conditions and their effects on the device performance. IETS(Inelastic Electron Tunneling Spectroscopy) is a promising technique for identifying defects in the gate dielectrics by detecting the small increase in current due to the interaction of tunneling electrons and defects in the gate oxide. I expect to find out the origin of the defects with IETS, also by help of SCA(surface charge analysis), ESR(electron spin resonance), and other conventional measurement techniques.

Kyung Hoae Koo
Research: Performance comparison between copper wire and future interconnects with new materials for on-chip communication below 22nm technology node.

Inter and Intra-chip communication, traditionally done using Cu interconnects, is becoming a severe bottleneck in performance enhancement. In order to solve the limits of conventional copper scheme for the future technology, Carbon nanotubes, Optical interconnects, and Surface plasmons are intensively investigated. My research is more focused on looking at their performance perspectives compared with copper interconnect technology. 3-D ICs with multiple active semiconductor layers is also a promising technique to improve information communication in a heterogeneous system. Vertical integration of devices would allow a substantial reduction in chip size; thus would limit the maximum required interconnect length resulting in reduced interconnect delay and power. However, the power density may increase requiring better heat removal techniques. I will also take a comprehensive look at the power/performance of the interconnects in 3-D heterogeneous systems.
URL: http://www.stanford.edu/~koo1028

Duygu Kuzum
Research: Interface-Engineering of Ge for High Mobility N- and P-FETs

Future CMOS scaling requires introduction of new channel materials and innovative device structures. Ge has been considered as a promising candidate as channel material for future technology nodes because of its lower effective conductivity mass. However, passivation of Ge interface has been a critical challenge. Ge NMOS in the past exhibited poor drive current and mobility by several demonstrations worldwide. Better characterization and understanding of interface traps and carrier scattering mechanisms are required to improve PMOS performance and to solve Ge NMOS problem. In this work, we are studying carrier scattering mechanisms and their effect on electron and hole mobility through low temperature electrical characterization. Conductance technique at low temperatures are being performed to get accurate distribution of Dit across the bandgap of Ge. With better understanding of the Ge interface we are developing techniques to improve the passivation of Ge interface by controlled ozone oxidation. The ozone oxidation technique should improve both electron and hole mobility.

Yeul Na
Research: Global Power/Performance Optimization for Transistors and Interconnects.

MooreÕs law and the accompanying scaling paradigm is facing tremendous challenges, most imminently from the so called Òpower wall.Ó The purpose of this project is to develop a sophisticated infrastructure for minimizing total power dissipation including transistors and interconnects. The infrastructure is specifically geared toward examining and comparing future novel technologies, in terms of systemÕs bottom line of power and delay.

Ali Kemal Okyay
Research: Metal-Semiconductor-Metal Photodetectors (MSM-PDs) in Group IV Semiconductors. (PhD Sept. 2007)

Optical clocking is promising to alleviate many limitations of large multi-GHz chips. Efficient detection in the low absorption regions (1.3-1.6 µm) of silica fibers and easy integration of photodetectors with Si-ICs are key aspects to realize on-chip optical clocking/signaling on dense integrated systems. III-V as well as Group IV semiconductors (like Ge) provide reasonably high detection efficiency in the range of interest. Amongst photodetector structures, MSM-PDs are attractive for their high sensitivity-bandwidth product, low capacitance and ease of integration. However, relatively large dark current poses additional power dissipation, an increasingly serious problem especially in today's already very hot chips. In this work, we present both theoretically and experimentally the application of asymmetric contact area on MSM-PDs to reduce dark current.

Jin Hong Park
Research: MILC (Metal-Induced Lateral Crystallization) on Ge for 3D IC

The purpose of this project is to get a well crystallized Ge in a low temperature(around 350C) process, which is MILC(Metal Induced Lateral Crystallization), since these crystallized films can be used as 2nd layer film in order to fabricate thin film transistors in 3D IC. Metals like gold and nickel are used as seeding agents to weaken a bonding energy in amorphous films. We are targeting to less than 0.1um CMOS TFTs with high mobility and low leakage on this single crystal Ge island.

Abhijit Jayant Pethe
Research: Germanium based Transistors for High Performance Logic AApplications (PhD March 2007)

Ultra-fast and reliable switching transistors have been the backbone of explosive growth in the semiconductor industry over the last few decades. This has been achieved mainly by continued scaling of transistor dimensions to achieve higher drive currents and higher switching speeds. However, with gate lengths presently scaling into the sub-50nm node, switching these devices off may pose a considerable challenge to the reliable operation of the transistor switch. One way to continue with enhanced device performance is with the introduction of novel materials in the channel to boost the drive currents without compromising the off state characteristics of the switch.

In the first part of this work, we are working on the performance limits of MOSFETs using various materials like Ge and III-Vs. Even though, many of these materials have a low effective mass for electrons providing for higher injection velocities, they also have a high dielectric constant and smaller bandgap making them susceptible to higher leakage and worse short channel effects. Ballistic transport simulations were performed for transistors with suitable architectures in the sub 20nm regime and were the materials were benchmarked for their efficacy as channel materials for NMOS. We have used models which take into account ballistic transport in the entire band structure including all conduction valleys, quantum effects in thin film structures, band-to- band tunneling and short-channel effects. Our results show that under normal operation a significant portion of the ON current in the III-V materials occurs through the heavier L-valleys, and hence they perform very similar to Ge. The effect of channel orientation on Ge ballistic performance is also discussed.

The second part of this work deals with fabrication and characterization of bulk Ge transistors. We have obtained higher electron and hole inversion mobilities in bulk-Ge transistors as compared to Si. The gate stack of thermally grown GeOxNy capped with CVD SiO2 was used. We have investigated the Dit at the gate interface using low temperature quasi-static and conductance measurements and report a low- interface trap density of 3-4XE^11 #/cm2. We also discuss the effect of surface orientation on the mobility and interface states at the gate interface. Replacing the source/drain region in the MOSFET with a metal of a suitable barrier height has been investigated as an avenue to increase performance by reducing the parasitic resistance in the device structure. We have characterized the barrier heights of various metals on the Ge interface. We report a low barrier height of ~100mV at the NiGe/Ge interface. We have successfully fabricated NiGe-based Schottky Source/Drain Ge transistors. We have also fabricated Si/Ge/Si heterostructures in the channel to increase the inversion layer mobility without adversely impacting the OFF state leakage. We have attempted to form a Schottky junction to this structure. This transistor provides an ideal avenue for scaling of PMOSFETs to the sub-25nm regime, by exploiting the excellent transport properties of inversion holes in Ge and the use of metal in the Source/Drain region to reduce the parasitic resistance.

Shyam Sunder Raghunathan
Research: Germanium n-channel Depletion-mode Double-gate FET

Germanium is considered a viable candidate to complement Silicon for high performance logic applications due to its increased hole and electron mobilities at low electric fields, compatibility with lower processing temperatures and smaller bandgap (conducive to supply voltage scaling). However, the conventional Ge NMOSFET has shown rather poor performance experimentally and the reason mostly ascribed to it is the poor quality of Ge-dielectric interface. In a depletion-mode device, the carriers are physically separated from the interface and hence are not expected to suffer from mobility degradation arising due to the interface. A double-gate (or multiple-gate) device ensures improved electrostatic behavior and compensates for the loss in subthreshold slope caused by buried-channel operation.

Sarves Verma
Research: Scalable Flash Memory with Engineered Tunnel Barrier Dielectric

The conventional Flash memory based on the ETOX cell with a floating gate faces two critical obstacles in the future: density and voltage scaling. Density is associated with scaling the gate length. The gate length cannot be reduced beyond a point because it requires a commensurate gate stack, specifically, tunnel oxide scaling for maintaining good gate control and short channel effects. However, the gate-tunnel oxide (GTO) reduction has a practical lower bound of ~ 7-9nm (depending upon NAND or NOR) due to leakage and data retention constraints. Below this GTO thickness, irrespective of how inter-poly dielectric (referred as ONO) is scaled, the electric field across it during charge retention increases, leading to unacceptable levels of tunneling current. The second major challenge with scaling is to reduce the programming and erase operation voltages. The usual operation voltages for these processes are greater than 6-8 volts, whereas, the supply voltages are much smaller. The difference is made up by using large charge pumps. As the supply voltages scale down according to MooreÕs law, while Flash operation voltages remain the same, it would become increasingly difficult to make efficient charge pumps. Hence, it is imperative for operation voltages to scale. Different voltages are demanded depending on whether the operation is write (programming and erasing) or read. Typically, read voltages are low, while erase and program operations stress the charge pump requirements and dictate the maximum voltages. The major impediment in erase voltage scaling is, once again, the inability to scale the gate oxide. The modern Flash uses Fowler Nordheim (F-N) tunneling erase mechanism through the channel. The current in F-N tunneling depends on the barrier height and the electric field.

The present work aims at engineering the tunnel barrier to overcome both the challenges mentioned above. We are doing this by looking at various engineered structures, at different dielectrics, finding the suitable dielectric with desired band offsets and finally understanding the charge trapping behavior of these high-k dielectrics.

Hyun-Yong Yu
Research: Low-loss Single Mode On-Chip Waveguides in Silicon

Optical interconnects present an attractive alternative for both clocking and signaling interconnects. In addition to the demand, the introduction of new materials such as Germanium (Ge) and high-k in mainstream CMOS line for transistors has opened doors and provided greater flexibility for a cost-effective integration of optics with Silicon. This represents an unprecedented confluence of demand and viability. However, significant technological hurdles must be overcome before optical interconnects become a cheap CMOS compatible technology. The focus must be to integrate all optical link components including transmitter, detector and transmission medium in Si or CMOS compatible materials. In this project, we concentrate on the transmission medium, specifically, proposing novel schemes to integrate very low-loss waveguides in Si.